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1/28 may 2002 m48t86 5.0v pc real time clock features summary n drop-in replacement for pc computer clock/calendar n counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation n interfaced with software as 128 ram locations: 14 bytes of clock and control registers 114 bytes of general purpose ram n selectable bus timing (intel/motorola) n three interrupts are separately software-maskable and testable time-of-day alarm (once/second to once/day) periodic rates from 122 m s to 500ms end-of-clock update cycle n programmable square wave output n 10 years of data retention and clock operation in the absence of power n self-contained battery and crystal in the caphat dip package n packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) n soic package provides direct connection for a snaphat top contains the battery and crystal n pin and function compatible with bq3285/7a and ds12887 figure 1. 24-pin pcdip, caphat ? package figure 2. 28-pin soic package 24 1 pcdip24 (pc) battery/crystal caphat 28 1 snaphat (sh) battery/crystal soh28 (mh)
m48t86 2/28 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....4 logic diagram (figure 3.) . ........................................................4 signal names (table 1.) . . . . . . . . . . . . . . . . . . . . . .....................................4 24-pin dip connections (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....5 28-pin soic connections (figure 5.) ................................................5 block diagram (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................5 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................6 absolute maximum ratings (table 2.) . . . .... ............................. ...........6 dc and ac parameters. . . . . . . . . . ........... .....................................7 operating and ac measurement conditions (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ac testing load circuit (no irq) (figure 7.) . . . . . .....................................7 ac testing load circuit (with irq) (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 capacitance (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dc characteristics (table 5.) . . . . . . ........... .....................................8 operation .... ..................................................................8 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 non-volatile ram . . . . . . . ........................................................9 intel bus read ac waveform (figure 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 intel bus write mode ac waveform (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........10 motorola bus read/write mode ac waveforms (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ac characteristics (table 6.) . . . . . . .......... .....................................11 clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............12 address map . . . . . . . . . . . . . . . . . . . ...............................................12 time, calendar, and alarm locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....12 address map (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....12 time, calendar, and alarm formats (table 7.) ........................................13 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................13 periodic interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............14 alarm interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................14 update cycle interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............14 oscillator control bits . . . . . . . . . . . . . . . . . ................................ ..........14 update cycle. . . . . . . . . . . . . . . . . . . . . . . . . . ........................................14 power down/up mode ac waveforms (figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power down/up mode ac characteristics (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power down/up trip points dc characteristics (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 square wave output selection . . . . . .......... .....................................16 square wave frequency/periodic interrupt rate (table 10.) . . . . . . . . . . . . . . ...............16
3/28 m48t86 register a . . . . . . ..............................................................17 register a (table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............17 update period timing and uip (figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....17 register b . . . . . . ..............................................................18 24/12 . . . . . . . . . . . . ........................................................ ....18 dse. daylight savings enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 register b (table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............18 update-ended/periodic interrupt relationship (figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................20 register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................20 register c (table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 register d (table 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 v cc noise and negative going transients. . . . . . . . . . . . . . . ......................... ...21 supply voltage protection (figure 16.) . . . . . . . ............................. ..........21 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........22 snaphat battery table (table 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............22 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 revision history. ..............................................................27
m48t86 4/28 summary description the m48t86 is an industry standard real time clock (rtc). the m48t86 is composed of a lithi- um energy source, quartz crystal, write protection circuitry, and a 128-byte ram array. this provides the user with a complete subsystem packaged in either a 24-pin dip caphat ? or 28-pin snaphat ? soic. functions available to the user include a non-volatile time-of-day clock, alarm in- terrupts, a one-hundred-year clock with program- mable interrupts, square wave output, and 128 bytes of non-volatile static ram. the 24-pin, 600mil dip caphat houses the m48t86 silicon with a quartz crystal and a long-life lithium button cell in a single package. the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat ? housing con- taining the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery packages are shipped sep- arately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the battery/crystal package part number is am4t28-br12sho (see table 16, page 22). figure 3. logic diagram table 1. signal names ai01640 e v cc m48t86 rcl rst v ss 8 ad0-ad7 mot r/w ds as irq sqw ad0-ad7 multiplexed address/data bus e chip enable input r/w write enable input ds data strobe input as address strobe input rst reset input rcl ram clear input mot bus type select input sqw square wave output irq interrupt request output (open drain) v cc supply voltage v ss ground nc not connected internally
5/28 m48t86 figure 4. 24-pin dip connections figure 5. 28-pin soic connections figure 6. block diagram ad4 ad5 ad6 nc ad1 ad2 ad3 nc ad0 sqw rst nc rcl nc nc irq ds as ad7 v ss e r/w mot v cc ai01641 m48t86 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 24 23 22 21 20 19 18 17 ai01642 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 24 23 1 ad4 ad5 ad6 nc ad1 ad2 ad3 ad0 sqw rst nc rcl nc nc irq ds as ad7 v ss e r/w mot v cc m48t86 nc nc nc nc 26 25 28 27 v ss ai01643 oscillator bcd/binary increment e /8 /64 /64 periodic interrupt/square wave selector square wave output power switch and write protect ad0-ad7 registers a,b,c,d clock calendar, and alarm ram storage registers (114 bytes) clock/ calendar update bus interface v cc v bat v cc pok ds r/w as sqw rst irq double buffered rcl
m48t86 6/28 maximum rating stressing the device above the rating listed in the aabsolute maximum ratingso table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260 c for 10 seconds (total thermal budget not to exceed 150 c for longer than 30 seconds). 2. for so package: reflow at peak temperature of 215 cto225 c for < 60 seconds (total thermal budget not to exceed 180 c for between 90 to 120 seconds). cauti on: negative undershoots below 0.3v are not allowed on any pin while in the battery back-up mode. cauti on: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) 40 to 85 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltages 0.3 to 7.0 v v cc supply voltage 0.3 to 7.0 v p d power dissipation 1 w
7/28 m48t86 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 7. ac testing load circuit (no irq) figure 8. ac testing load circuit (with irq) table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25 c, f = 1mhz. 3. outputs deselected. parameter m48t86 unit supply voltage (v cc ) 4.5 to 5.5 v ambient operating temperature (t a ) 0to70 c load capacitance (c l ) 100 pf input rise and fall times 5ns input pulse voltages 0 to 3 v input and output timing ref. voltages 1.5 v ai01644 5v 50pf 960 w for all outputs except irq 510 w ai01645 5v 130pf 1.15k w irq symbol parameter (1,2) min max unit c in input capacitance 7 pf c io (3) input / output capacitance 5 pf
m48t86 8/28 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5v (except where noted). 2. outputs deselected. operation automatic deselection of the device ensures the data integrity is not compromised should v cc fall below specified power-fail deselect voltage (v pfd ) levels (see figure 13, page 15). the auto- matic deselection of the device remains in effect upon power up for a period of 200ms (max) after v cc rises above v pfd , provided that the real time clock is running and the count-down chain is not reset. this allows sufficient time for v cc to sta- bilize and gives the system clock a wake-up period so that a valid system reset can be established. the block diagram in figure 6, page 5 shows the pin connections and the major internal functions of the m48t86. signal description v cc ,v ss . dc power is provided to the device on these pins.the m48t86 uses a 5v v cc . sqw (square wave output). during normal op- eration (e.g., valid v cc ), the sqw pin can output a signal from one of 13 taps. the frequency of the sqw pin can be changed by programming regis- ter a as shown in table 10, page 16. the sqw signal can be turned on and off using the sqwe bit (register b; bit 3). the sqw signal is not avail- able when v cc is less than v pfd . ad0-ad7 (multiplexed bi-directional address/ data bus). the m48t86 provides a multiplexed bus in which address and data information share the same signal path. the bus cycle consists of two stages; first the address is latched, followed by the data. address/data multiplexing does not slow the access time of the m48t86, because the bus change from address to data occurs during the in- ternal ram access time. addresses must be valid prior to the falling edge of as (see figure 9, page 9), at which time the m48t86 latches the address present on ad0-ad7. valid write data must be present and held stable during the latter portion of the r/w pulse (see figure 10, page 10). in a read cycle, the m48t86 outputs 8 bits of data during the latter portion of the ds pulse. the read cycle is terminated and the bus returns to a high impedance state upon a high transition on r/ w. as (address strobe input). a positive going pulse on the address strobe (as) input serves to demultiplex the bus. the falling edge of as causes the address present on ad0-ad7 to be latched within the m48t86. mot (mode select). the mot pin offers the flex- ibility to choose between two bus types (see fig- ure 11, page 10). when connected to v cc , motorola bus timing is selected. when connected to v ss or left disconnected, intel bus timing is se- lected. the pin has an internal pull-down resis- tance of approximately 20k w . ds (data strobe input). the ds pin is also re- ferred to as read (rd). a falling edge transition on the data strobe (ds) input enables the output during a a read cycle. this is very similar to an output enable (g) signal on other memory devic- es. symbol parameter test condition (1) min max unit i li input leakage current 0v v in v cc 1 m a i lo (2) output leakage current 0v v out v cc 1 m a i cc supply current outputs open 15 ma v il input low voltage 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol =4ma 0.4 v output low voltage (irq) i ol = 0.5ma 0.4 v v oh output high voltage i oh = 1ma 2.4 v
9/28 m48t86 e (chip enable input). the chip enable pin must be asserted low for a bus cycle in the m48t86 to be accessed. bus cycles which take place without asserting e will latch the addresses present, but no data access will occur. irq (interrupt request output). the irq pin is an open drain output that can be used as an inter- rupt input to a processor. the irq output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. irq returns to a high impedance state whenever register c is read. the rst pin can also be used to clear pending interrupts. the irq bus is an open drain output so it requires an exter- nal pull-up resistor to v cc . rst (reset input). the m48t86 is reset when the rst input is pulled low. with a valid v cc ap- plied and a low on rst, the following events oc- cur: 1. periodic interrupt enable (pie) bit is cleared to a zero (register b; bit 6); 2. alarm interrupt enable (aie) bit is cleared to a zero (register b; bit 5); 3. update ended interrupt request (uf) bit is cleared to a zero (register c; bit 4); 4. interrupt request (irqf) bit is cleared to a zero (register c bit 7); 5. periodic interrupt flag (pf) bit is cleared to a zero (register c; bit 6); 6. the device is not accessible until rst is re- turned high; 7. alarm interrupt flag (af) bit is cleared to a zero (register c; bit 5); 8. the irq pin is in the high impedance state 9. square wave output enable (sqwe) bit is cleared to zero (register b; bit 3); and 10.update ended interrupt enable (uie) is cleared to a zero (register b; bit 4). rcl (ram clear). the rcl pin is used to clear all 114 storage bytes, excluding clock and control registers, of the array to ff(hex) value. the array will be cleared when the rcl pin is held low for at least 100ms with the oscillator running. usage of this pin does not affect battery load. this function is applicable only when v cc is applied. r/w (read/write input). the r/w pin is used to latch data into the m48t86 and provides func- tionality similar to w in other memory systems. non-volatile ram the 114 general-purpose non-volatile ram bytes are not dedicated to any special function within the m48t86. they can be used by the processor pro- gram as non-volatile memory and are fully acces- sible during the update cycle. figure 9. intel bus read ac waveform ai01647 tcyc tasd tasw as e ad0-ad7 tdsl tdsh tdas tcs tod tch tas tah tdhr ds r/w
m48t86 10/28 figure 10. intel bus write mode ac waveform figure 11. motorola bus read/write mode ac waveforms ai01648 tcyc tasd tasw as e ad0-ad7 tdsl tdsh tdas tcs tdw tch tas tah tdhw ds r/w ai01649 tasd tasw as e ad0-ad7 (write) tcyc tdsh tdas tcs trwh tas tdhw ds r/w tdsl trws tch ad0-ad7 (read) tdw tah tah tas tod tdhr
11/28 m48t86 table 6. ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5v (except where noted). 2. see table 10, page 16. symbol parameter (1) m48t86 unit min typ max t cyc cycle time 160 ns t dsl pulse width, data strobe low or r/w high 80 ns t dsh pulse width, data strobe high or r/w low 55 ns t rwh r/w hold time 0 ns t rws r/w setup time 10 ns t cs chip select setup time 5 ns t ch chip select hold time 0 ns t dhr read data hold time 0 25 ns t dhw write data hold time 0 ns t as address setup time 20 ns t ah address hold time 5 ns t das delay time, data strobe to address strobe rise 10 ns t asw pulse width address strobe high 30 ns t asd delay time, address strobe to data strobe rise 35 ns t od output data delay time from data strobe rise 50 ns t dw write setup time 30 ns t buc delay time before update cycle 244 m s t pi (2) periodic interrupt time interval t uc time of update cycle 1 m s
m48t86 12/28 clock operations address map the address map of the m48t86 is shown in fig- ure 12. it consists of 114 bytes of user ram, 10 bytes of ram that contain the rtc time, calendar and alarm data, and 4 bytes which are used for control and status. all bytes can be read or written to except for the following: 1. registers c & d are aread only.o 2. bit 7 of register a is aread only.o the contents of the four registers a, b, c, and d are described in the aregisterso section. time, calendar, and alarm locations the time and calendar information is obtained by reading the appropriate memory bytes. the time, calendar, and alarm registers are set or initialized by writing the appropriate ram bytes. the con- tents of the time, calendar, and alarm bytes can be either binary or binary-coded decimal (bcd) for- mat. before writing the internal time, calendar, and alarm register, the set bit (register b; bit 7) should be written to a logic '1.' this will prevent up- dates from occurring while access is being at- tempted. in addition to writing the time, calendar, and alarm registers in a selected format (binary or bcd), the data mode (dm) bit (register b; bit 2), must be set to the appropriate logic level ('1' signi- fies binary data; '0' signifies binary coded decimal (bcd data). all time, calendar, and alarm bytes must use the same data mode. the set bit should be cleared after the data mode bit has been written to allow the real time clock to up- date the time and calendar bytes. once initialized, the real time clock makes all updates in the se- lected mode. the data mode cannot be changed without reinitializing the ten data bytes. table 7, page 13 shows the binary and bcd formats of the time, calendar, and alarm locations. the 24/12 bit (register b; bit 1) cannot be changed without rein- itializing the hour locations. when the 12-hour for- mat is selected, a logic '1' in the high order bit of the hours byte represents pm. the time, calendar, and alarm bytes are always accessible because they are double-buffered. once per second the ten bytes are advanced by one second and checked for an alarm condition. if a read of the time and calendar data occurs during an update, a problem exists where data such as seconds, minutes, or hours may not correlate. however, the probability of reading incorrect time and calendar data is low. methods of avoiding possible incorrect time and calendar reads are reviewed later in this text. figure 12. address map ai01650 seconds seconds alarm minutes minutes alarm hours hours alarm day of week date of month month year register a register b register c register d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 bcd or binary format 00 0d 0e 7f 0 13 14 127 114 bytes 14 bytes clock and control status registers storage registers
13/28 m48t86 table 7. time, calendar, and alarm formats interrupts the rtc plus ram includes three separate, fully automatic sources of interrupt (alarm, periodic, up- date-in-progress) available to a processor. the alarm interrupt can be programmed to occur at rates from once per second to once per day. the periodic interrupt can be selected from rates of 500ms to 122 m s. the update-ended interrupt can be used to indicate that an update cycle has com- pleted. the processor program can select which inter- rupts, if any, are going to be used. three bits in register b enable the interrupts. writing a logic '1' to an interrupt-enable bit (register b; bit 6 = pie; bit 5 = aie; bit 4 = uie) permits an interrupt to be initialized when the event occurs. a '0' in an inter- rupt-enable bit prohibits the irq pin from being as- serted from that interrupt condition. if an interrupt flag is already set when an interrupt is enabled, irq is immediately set at an active level, although the interrupt initiating the event may have occurred much earlier. as a result, there are cases where the program should clear such earlier initiated in- terrupts before first enabling new interrupts. when an interrupt event occurs, the related flag bit (register c; bit 6 = pf; bit 5 = af; bit 4 = uf) is set to a logic '1.' these flag bits are set indepen- dent of the state of the corresponding enable bit in register b and can be used in a polling mode with- out enabling the corresponding enable bits. the interrupt flag bits are status bits which software can interrogate as necessary. when a flag is set, an indication is given to soft- ware that an interrupt event has occurred since the flag bit was last read; however, care should be tak- en when using the flag bits as all are cleared each time register c is read. double latching is includ- ed with register c so that bits which are set re- main stable throughout the read cycle. all bits which are set high are cleared when read. any new interrupts which are pending during the read cycle are held until after the cycle is completed. one, two, or three bits can be set when reading register c. each utilized flag bit should be exam- ined when read to ensure that no interrupts are lost. the second flag bit usage method is with fully en- abled interrupts. when an interrupt flag bit is set and the corresponding enable bit is also set, the irq pin is asserted low. irq is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. the irqf bit (reg- ister c; bit 7) is a '1' whenever the irq pin is being driven low. determination that the rtc initiated an interrupt is accomplished by reading register c. a logic '1' in the irqf bit indicates that one or more interrupts have been initiated by the m48t86. the act of reading register c clears all active flag bits and the irqf bit. address rtc bytes range decimal binary bcd 0 seconds 0-59 00-3b 00-59 1 seconds alarm 0-59 00-3b 00-59 2 minutes 0-59 00-3b 00-59 3 minutes alarm 0-59 00-3b 00-59 4 hours, 12-hrs 1-12 01-0c am 81-8c pm 01-12 am 81-92 pm hours, 24-hrs 0-23 00-17 00-23 5 hours alarm, 12-hrs 1-12 01-0c am 81-8c pm 01-12 am 81-92 pm hours alarm, 24-hrs 0-23 00-17 00-23 6 day of week (1 = sun) 1-7 01-07 01-07 7 day of month 1-31 01-1f 01-31 8 month 1-12 01-0c 01-12 9 year 0-99 00-63 00-99
m48t86 14/28 periodic interrupt the periodic interrupt will cause the irq pin to go to an active state from once every 500ms to once every 122 m s. this function is separate from the alarm interrupt which can be output from once per second to once per day. the periodic interrupt rate is selected using the same register a bits which select the square wave frequency (see table 10, page 16). changing the register a bits affects both the square wave frequency and the periodic interrupt output. however, each function has a separate enable bit in register b. the periodic in- terrupt is enabled by the pie bit (register b; bit 6). the periodic interrupt can be used with software counters to measure inputs, create output inter- vals, or await the next needed software function. alarm interrupt the alarm interrupt provides the system processor with an interrupt when a match is made between the rtc's hours, minutes, and seconds bytes and the corresponding alarm bytes. the three alarm bytes can be used in two ways. first, when the alarm time is written in the appro- priate hours, minutes, and seconds alarm loca- tions, the alarm interrupt is initiated at the specified time each day if the alarm interrupt enable bit (register b; bit 5) is high. the second use is to in- sert a adon't careo state in one or more of the three alarm bytes. the adon't careo code is any hexa- decimal value from c0 to ff. the two most signif- icant bits of each byte set the adon't careo condition when at logic '1.' an alarm will be gener- ated each hour when the adon't careo is are set in the hours byte. similarly, an alarm is generated every minute with adon't careo codes in the hour and minute alarm bytes. the adon't careo codes in all three alarm bytes create an interrupt every sec- ond. update cycle interrupt after each update cycle, the update cycle ended flag bit (uf) (register c; bit 4) is set to a '1.' if the update interrupt enable bit (uie) (register b; bit 4) is set to a '1,' and the set bit (register b; bit 7) is a '0,' then an interrupt request is generated at the end of each update cycle. oscillator control bits when the m48t86 is shipped from the factory the internal oscillator is turned off. this feature pre- vents the lithium energy cell from being dis- charged until it is installed in a system. a pattern of a010o in bits 4-6 of register a will turn the oscillator on and enable the countdown chain. a pattern of a11xo will turn the oscillator on, but holds the countdown chain of the oscillator in reset. all other combinations of bits 4-6 keep the oscillator off. update cycle the m48t86 executes an update cycle once per second regardless of the set bit (register b; bit 7). when the set bit is asserted, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time in- crements. however, the time countdown chain continues to update the internal copy of the buffer. this feature allows accurate time to be main- tained, independent of reading and writing the time, calendar, and alarm buffers. this also guar- antees that the time and calendar information will be consistent. the update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a adon't careo code is present in all three positions. there are three methods of accessing the real time clock that will avoid any possibility of obtain- ing inconsistent time and calendar data. the first method uses the update-ended interrupt. if en- abled, an interrupt occurs after every update cycle which indicates that over 999ms are available to read valid time and date information. if this inter- rupt is used, the irqf bit (register c; bit 7) should be cleared before leaving the interrupt routine. a second method uses the update-in-progress (uip) bit (register a; bit 7) to determine if the up- date cycle is in progress. the uip bit will pulse once per second. after the uip bit goes high, the update transfer occurs 244 m s later. if a low is read on the uip bit, the user has at least 244 m s before the time/calendar data will be changed. therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244 m s. the third method uses a periodic interrupt to deter- mine if an update cycle is in progress. the uip bit is set high between the setting of the pf bit (reg- ister c; bit 6). periodic interrupts that occur at a rate greater than t buc allow valid time and date in- formation to be reached at each occurrence of the periodic interrupt.the reads should be complet- ed within 1/(t pl/2 +t buc ) to ensure that data is not read during the update cycle.
15/28 m48t86 figure 13. power down/up mode ac waveforms table 8. power down/up mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5v (except where noted). 2. v cc fall time of less than t f may result in deselection/write protection not occurring until 200 m s after v cc passes v pfd . table 9. power down/up trip points dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5v (except where noted). 2. all voltages referenced to v ss . 3. at 25 c. symbol parameter (1) min max unit t f (2) v cc fall time 300 m s t r v cc rise time 100 m s t rec v pfd to e high 20 200 ms symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage 4.0 4.35 v v so battery back-up switchover voltage 3.0 v t dr (3) expected data retention time 10 years ai01646 v cc e tf tr trec 4.5v v pfd v so
m48t86 16/28 square wave output selection thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block dia- gram of figure 6, page 5. the purpose of selecting a divider tap is to generate a square wave output signal on the sqw pin. the rs3-rs0 bits in reg- ister a establish the square wave output frequen- cy. these frequencies are listed in table 10, page 16. the sqw frequency selection shares the 1-of- 15 selector with the periodic interrupt generator. once the frequency is selected, the output of the sqw pin can be turned on and off under program control with the square wave enabled (sqwe) bit. table 10. square wave frequency/periodic interrupt rate register a bits square wave periodic interrupt rs3 rs2 rs1 rs0 frequency units period units 0000 none none 0001256hz3 .90625 ms 0010128hz 7.8125 ms 0011 8.192 khz 122.070 us 0100 4.096 khz 244.141 us 0101 2.048 khz 488.281 us 0110 1.024 khz 976.5625 us 0111512hz 1.953125 ms 1000256hz3 .90625 ms 1001128hz 7.8125 ms 101064hz 15.625 ms 101132hz 31.25 ms 110016hz 62.5 ms 11018hz125ms 11104hz250ms 11112hz500ms
17/28 m48t86 register a uip. update in progress. the update in progress (uip) bit is a status flag that can be mon- itored. when the uip bit is '1,' the update transfer will soon occur (see figure 14). when uip is a '0,' the update transfer will not occur for at least 244 m s. the time, calendar, and alarm information in ram is fully available for access when the uip bit is '0.' the uip bit is aread onlyo and is not af- fected by rst. writing the set bit in register b to a '1' inhibits any update transfer and clears the uip status bit. osc0, osc1, osc2. oscillator control. these three bits are used to control the oscillator and re- set the countdown chain. a pattern of a010o en- ables operation by turning on the oscillator and enabling the divider chain. a pattern of 11x turns the oscillator on, but keeps the frequency divider disabled. when a010o is written, the first update begins after 500ms. rs3, rs2, rs1, rs0. these four rate-selection bits select one of the 13 taps on the 15-stage di- vider or disable the divider output. the tap select- ed may be used to generate an output square wave (sqw pin) and/or a periodic interrupt. the user may do one of the following: 1. enable the interrupt with the pie bit; or 2. enable the sqw output with the sqwe bit; or 3. enable both at the same time and same rate; or 4. enable neither. table 10, page 16 lists the periodic interrupt rates and the square wave frequencies that may be cho- sen with the rs bits. these four read/write bits are not affected by rst. table 11. register a msb figure 14. update period timing and uip bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 uip osc2 osc1 osc0 rs3 rs2 rs1 rs0 ai01651 uip update period (1sec) tbuc tuc
m48t86 18/28 register b set. when the set bit is a '0,' the update trans- fer functions normally by advancing the counts once per second. when the set bit is written to a '1,' any update transfer is inhibited and the pro- gram may initialize the time and calendar bytes without an update occurring. read cycles can be executed in a similar manner. set is a read/ write bit which is not modified by rst or internal functions of the m48t86. pie: periodic interrupt enable. the periodic in- terrupt enable bit (pie) is a read/write bit which allows the periodic interrupt flag (pf) bit in register c to cause the irq pin to be driven low (see figure 15, page 19 for the relationship be- tween pie and uie). when the pie bit is set to '1,' periodic interrupts are generated by driving the irq pin low at a rate specified by the rs3-rs0 bits of register a. a '0' in the pie bit blocks the irq output from being driven by a periodic inter- rupt, but the periodic flag (pf) bit is still set at the periodic rate. pie is not modified by any internal m48t86 functions, but is cleared to '0' on rst. aie: alarm interrupt enable. the alarm inter- rupt enable (aie) bit is a read/write bit which, when set to a '1,' permits the alarm flag (af) bit in register c to assert irq. an alarm interrupt oc- curs for each second that the three time bytes equal the three alarm bytes including a adon't careo alarm code of binary 1xxxxxxx. when the aie bit is set to '0,' the af bit does not initiate the irq signal. the rst pin clears aie to '0.' the in- ternal functions of the m48t86 do not affect the aie bit. uie: update ended interrupt enable. the up- date ended interrupt enable (uie) bit is a read/ write bit which enables the update end flag (uf) bit in register c to assert irq. a transition low on the rst pin or the set bit going high clears the uie bit. sqwe: square wave enable. when the square wave enable (sqwe) bit is set to a '1,' a square wave signal is driven out on the sqw pin. the fre- quency is determined by the rate-selection bits rs3-rs0. when the sqwe bit is set to '0,' the sqw pin is held low. the sqwe bit is cleared by the rst pin. sqwe is a read/write bit. dm: data mode. the data mode (dm) bit indi- cates whether time and calendar information are in binary or bcd format. the dm bit is set by the pro- gram to the appropriate format and can be read as required. this bit is not modified by internal func- tion or rst. a '1' in dm signifies binary data and a '0' specifies binary coded decimal (bcd) data. 24/12 the 24/12 control bit establishes the format of the hours byte. a '1' indicates the 24-hour mode and a '0' indicates the 12-hour mode. this bit is read/ write and is not affected by internal functions or rst. dse. daylight savings enable the daylight savings enable (dse) bit is a read/ write bit which enables two special updates when set to a '1.' on the first sunday in april, the time increments from 1:59:59am to 3:00:00 am. on the last sunday in october, when the time reaches 1:59:59 am, it changes to 1:00:00 am. these special updates do not occur when the dse bit is a '0.' this bit is not affected by internal func- tions or rst. table 12. register b msb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 set pie aie uie sqwe dm 24/12 dse
19/28 m48t86 figure 15. update-ended/periodic interrupt relationship ai01652b uip update period (1sec) pf uf tpi tpi tpi tbuc tuc
m48t86 20/28 register c irqf: interrupt request flag. the interrupt re- quest flag (irqf) bit is set to a '1' when one or more of the following are true: pf = pie = 1 af = aie = 1 uf = uie = 1 (e.g., irqf = pf*pie+af*aie+uf*uie) pf: periodic interrupt flag. the periodic inter- rupt flag (pf) is a aread onlyo bit which is set to a '1' when an edge is detected on the selected tap of the divider chain. the rs3-rs0 bits establish the periodic rate. pf is set to a '1' independent of the state of the pie bit. the irq signal is active and will set the irqf bit. the pf bit is cleared by a rst or a software read of register c. af: alarm flag. a '1' in the af (alarm interrupt flag) bit indicates that the current time has matched the alarm time. if the aie bit is also a '1,' the irq pin will go low and a '1' will appear in the irqf bit. a rst or a read of register c will clear af. uf: update ended interrupt flag. the update ended interrupt flag (uf) bit is set after each up- date cycle. when the uie bit is set to a '1,' the '1' in the uf bit causes the irqf bit to be a '1.' this will assert the irq pin. uf is cleared by reading register c or a rst. bit 0 through 3: unused bits. bit 3 through bit 0 are unused. these bits always read '0' and can- not be written. register d vrt: valid ram and time. the valid ram and time (vrt) bit is set to the '1' state by stmicro- electronics prior to shipment. this bit is not writ- able and should always be a '1' when read. if a '0' is ever present, an exhausted internal lithium cell is indicated and both the contents of the rtc data and ram data are questionable. this bit is unaf- fected by rst. bit 0 through 6: unused bits. the remaining bits of register d are not usable. they cannot be written and when read, they will always read '0.' table 13. register c msb table 14. register d msb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 irqfpfafuf0000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vrt0000000
21/28 m48t86 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1 m f (as shown in figure 16) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 16. supply voltage protection ai02169 v cc 0.1 m f device v cc v ss
m48t86 22/28 part numbering table 15. ordering information scheme note: 1. the soic package (soh28) requires the battery/crystal package (snaphat ? ) which is ordered separately under the part number am4t28-br12sho in plastic tube or am4t28-br12shtro in tape & reel form. caution : do not place the snapha t battery package am4txx-br12sho in conductive foam as it will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest you. table 16. snaphat battery table example: m48t 86 mh 1 tr device type m48t supply voltage and write protect voltage 86 = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v package pc = pcdip24 mh (1) = soh28 temperature range 1=0to70 c shipping method for soic blank = tubes tr = tape & reel part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh
23/28 m48t86 package mechanical information figure 17. pcdip24 24-pin plastic dip, battery caphat, package outline note: drawing is not to scale. table 17. pcdip24 24-pin plastic dip, battery caphat, package mechanical data symb mm inches typ min max typ min max a 8.89 9.65 0.3500 0.3799 a1 0.38 0.76 0.0150 0.0299 a2 8.36 8.89 0.3291 0.3500 b 0.38 053 0.0150 0.0209 b1 1.14 1.78 0.0449 0.0701 c 0.20 0.31 0.0079 0.0122 d 34.29 34.80 1.3500 1.3701 e 17.83 18.34 0.7020 0.7220 e1 2.29 2.79 0.0902 0.1098 e3 25.15 30.73 0.9902 1.2098 ea 15.24 16.00 0.6000 0.6299 l 3.05 3.81 0.1201 0.1500 n24 24 pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3
m48t86 24/28 figure 18. soh28 28-lead plastic small outline, 4-socket snaphat, package outline note: drawing is not to scale. table 18. soh28 28-lead plastic small outline, 4-socket battery snaphat, package mechanical data symb mm inches typ min max typ min max a 3.05 0.1201 a1 0.05 0.36 0.0020 0.0142 a2 2.34 2.69 0.0921 0.1059 b 0.36 0.51 0.0142 0.0201 c 0.15 0.32 0.0059 0.0126 d 17.71 18.49 0.6972 0.7280 e 8.23 8.89 0.3240 0.3500 e 1.27 0.0500 eb 3.20 3.61 0.1260 0.1421 h 11.51 12.70 0.4531 0.5000 l 0.41 1.27 0.0161 0.0500 a 0 8 0 8 n28 28 cp 0.10 0.0039 soh-a e n d c l a1 a 1 h a cp be a2 eb
25/28 m48t86 figure 19. sh 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 19. sh 4-pin snaphat housing for 48mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 9.78 0.3850 a1 6.73 7.24 0.2650 0.2850 a2 6.48 6.99 0.2551 0.2752 a3 0.38 0.0150 b 0.46 0.56 0.0181 0.0220 d 21.21 21.84 0.8350 0.8598 e 14.22 14.99 0.5598 0.5902 ea 15.55 15.95 0.6122 0.6280 eb 3.20 3.61 0.1260 0.1421 l 2.03 2.29 0.0799 0.0902 sh a1 a d e ea eb a2 b l a3
m48t86 26/28 figure 20. sh 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 20. sh 4-pin snaphat housing for 120mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
27/28 m48t86 revision history table 21. document revision history date revision details march 1999 first issue 05/04/00 page layout changed 07/31/01 reformatted; temp/voltage info. added to tables (table 5, 6, 8, 9) 05/20/02 modify reflow time and temperature footnotes (table 2)
m48t86 28/28 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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